1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device with electrically rewritable memory cells each having a carrier storage layer provided between a semiconductor substrate and a control gate.
2. Description of the Related Art
A semiconductor memory device having MOSFET structure type memory cells with floating gates or MNOS structure type memory cells capable of data writing and electrically erasing operations have been known widely as the electrically erasable programmable read-only memory, or "EEPROM," for short. The memory array of such kind of EEPROM may be constituted by arranging memory cells so that these cells are respectively positioned at crossing points between parallel row lines and parallel column lines to provide a matrix cell arrangement. In a presently available EEPROM, drains of every two neighboring memory cells are formed together as a common drain layer, with which a corresponding column line is in electrically contact, thereby to decrease the necessary cell area on a chip substrate. With such an arrangement, however, the total integration density of memory cells in EEPROM cannot be improved as highly as required, since the electrical contact section still occupies relatively large part of the chip substrate.
Recently, an advanced EEPROM has been proposed which has memory cell units each of which consists of a series array of a preselected number of data storage transistors. Such memory cell units are called the "NAND type cell" or "NAND cell unit." With the NAND cell arrangement, the contact sections can be decreased in number greatly. The effective memory area can thus be increased to improve the total integration density of EEPROM.
The NAND cell type EEPROM, however, still suffers from insufficiency in large-capacity data storage performance, for the following reasons. In the conventional NAND type EEPROM, driver circuits are respectively connected with control gate lines, also known as the "word lines," of memory cell transistors in each NAND cell unit. The control gate drive circuit in the NAND cell type EEPROM is more complicated and larger in size than the conventional EEPROM. This is because data writing and erasing operations in this EEPROM are not so simple as in the conventional EEPROM. Complicated data accessing scheme requires high-performance control gate drive circuit configuration, which is naturally increased in size. Increasing in size of the control gate drive circuit will cause the effective memory area on the chip substrate to be decreased, even if the NAND cell arrangement is utilized in order to decrease the contact sections in the memory cells. As a result, it cannot be expected that the memory integration density is enhanced even in the NAND cell type EEPROM.